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Daeyeon Kim

Ph.D candiate (Postech)

Education

BS. from Computer Science & Engineering

Ulsan National Institute of Science and Technology (UNIST)
2011 - 2018

MS. from Electrical Engineering

Pohang University of Science and Technology (POSTECH)
2018 - 2020

Dr.-Ing from Electrical Engineering

Pohang University of Science and Technology (POSTECH)
2020 -

Languages

  • Korean (Native)
  • English (Advanced)

Interests

  • Physical Design Automation
  • Floorplan/Powerplan Optimization
  • Machine Learning in EDA
  • Routing

About Theme

Career Profile

Daeyeon Kim is currently a Ph.D candidate in the Department of Electrical Engineering,Postech. My research interests are routing algorithm in physical design and machine learning in EDA. I specialize in programming based on C/C++/Phython/Tcl.

Experiences

Graduate Student Researcher

2016 - Present
Postech, Pohang, Republic of Korea
  • Thesis: Routing ALgorithm and Routability Analysis in Verty-large-scale Integration

Research Internship

Dec. 2017 - Feb. 2015
VLSI CAD Lab., University of California, San Diego

Undergraduated Sutudent Researcher

Oct. 2016 - Feb. 2018
UNIST, Ulsan, Republic of Korea

Projects

Obstacle Avoiding Topology-aware Bus Router -
LEF/DEF Based Global Router - A responsive website template designed to help web developers/designers market their services.
LEF/DEF Based Initial Detailed Router - A responsive website template designed to help startups promote their products or services and to attract users & investors
Artificial Netlist Generator for Machine Learning Application in EDA - A comprehensive website template solution for startups/developers to market their mobile apps.
Self-Driving Vehicle Routing Algorithm Simulator -

Publications

  • Compact Topology-aware Bus Routing for Design Regularity
    • Daeyeon Kim, Sanggi Do, Sung-Yun Lee and Seokhyeong Kang
    IEEE Transaction on Computer-Aided Design of Integrated Circuit and Systems (2020)
  • Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator (to appear)
    • Daeyeon Kim, Hyunjeong Kwon, Sung-Yun Lee, Seungwon Kim, Mingyu Woo and Seokhyeong Kang
    Proceedings Design, Automation and Test in Europe (2021)
  • Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction
    • Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang and Byoung Hun Lee
    IEEE International Symposium on Multiple-Valued Logic (2020)

    Skills & Proficiency

    Python

    Tensorflow, Keras, Pytorch

    C/C++ Programming

    Objective-C / Swift (IOS Programming)

    C/C++ Programming

    Verilog

    Innovus Implementation System

    IC Compiler II